TY - JOUR
AU1 - Lee, Honggoo
AU2 - Han, Sangjun
AU3 - Kim, Youngsik
AU4 - Kim, Myoungsoo
AU5 - Heo, Hoyoung
AU6 - Jeon, Sanghuck
AU7 - Choi, DongSub
AU8 - Nabeth, Jeremy
AU9 - Brinster, Irina
AU1 - Pierson, Bill
AU1 - Robinson, John C.
AB - Advancing technology nodes with smaller process margins require improved photolithography overlay control. Overlay control at develop inspection (DI) based on optical metrology targets is well established in semiconductor manufacturing. Advances in target design and metrology technology have enabled significant improvements in overlay precision and accuracy. One approach to represent in-die on-device as-etched overlay is to measure at final inspection (FI) with a scanning electron microscope (SEM). Disadvantages to this approach include inability to rework, limited layer coverage due to lack of transparency, and higher cost of ownership (CoO). A hybrid approach is investigated in this report whereby infrequent DI/FI bias is characterized and the results are used to compensate the frequent DI overlay results. The bias characterization is done on an infrequent basis, either based on time or triggered from change points. On a per-device and per-layer basis, the optical target overlay at DI is compared with SEM on-device overlay at FI. The bias characterization results are validated and tracked for use in compensating the DI APC controller. Results of the DI/FI bias characterization and sources of variation are presented, as well as the impact on the DI correctables feeding the APC system. Implementation details in a high volume manufacturing (HVM) wafer fab will be reviewed. Finally future directions of the investigation will be discussed.
TI - Device overlay method for high volume manufacturing
JF - Proceedings of SPIE
DO - 10.1117/12.2219701
DA - 2016-03-18
UR - https://www.deepdyve.com/lp/spie/device-overlay-method-for-high-volume-manufacturing-0x9LBlu0Ty
SP - 97781F
EP - 97781F-6
VL - 9778
IS - 
DP - DeepDyve
ER -