TY - JOUR
AU - 
TI - Global Wiring by Simulated Annealing
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DO - 10.1109/tcad.1983.1270039
DA - 1983-10-01
UR - https://www.deepdyve.com/lp/crossref/global-wiring-by-simulated-annealing-SW6q9Z8zxS
SP - 215
EP - 222
VL - 2
IS - 4
DP - DeepDyve
ER -