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Optimization of VDD and VTH for low-power and high speed applications

Optimization of VDD and VTH for low-power and high speed applications Optimization of VDD and VTH for Low-Power and High-Speed Applications Koichi Nose and Takayasu Sakurai Institute of Industrial Science, University of Tokyo 7-22-1 Roppongi, Minato-ku, Tokyo, 106-8558 Japan Tel: +81-3-3403-1643 Fax: +81-3-3403-1649 e-mail: {nose, tsakurai}@ iis.u-tokyo.ac.jp Abstract - Closed-form formulas are presented for optimum supply voltage (VDD) and threshold voltage (VTH) that minimize power dissipation when technology parameters and required speed are given. The formulas take into account short-channel effects and the variation of VTH and temperature. Using typical device parameters, it is shown that a simple guideline to optimize the power consumption is to set the ratio of maximum leakage power to total power about 30%. Extending the analysis, the future VLSI design trend is discussed. The optimum VDD coincides with the SIA roadmap and the optimum VTH for logic blocks at the highest temperature and at the lowest process variation corner is in the range of 0V~ 0.1V over generations. 10-4 10-5 Drain current [A] 10-6 L=0.5 m Measured 10-7 Conventional ( =1.57 V =0.27) TH Proposed formula ( =1.5 V =0.29) TH 0 0.5 1 Gate voltage [V] 1.5 I. Introduction Decreasing power consumption of VLSI's is getting one of the key design issues. Lowering http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

Optimization of VDD and VTH for low-power and high speed applications

Nose, Koichi; Sakurai, Takayasu
Association for Computing Machinery — Jan 28, 2000
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Datasource
Association for Computing Machinery
Copyright
Copyright © 2000 by ACM Inc.
ISBN
0-7803-5974-7
doi
10.1145/368434.368755
Publisher site
See Article on Publisher Site

Abstract

Optimization of VDD and VTH for Low-Power and High-Speed Applications Koichi Nose and Takayasu Sakurai Institute of Industrial Science, University of Tokyo 7-22-1 Roppongi, Minato-ku, Tokyo, 106-8558 Japan Tel: +81-3-3403-1643 Fax: +81-3-3403-1649 e-mail: {nose, tsakurai}@ iis.u-tokyo.ac.jp Abstract - Closed-form formulas are presented for optimum supply voltage (VDD) and threshold voltage (VTH) that minimize power dissipation when technology parameters and required speed are given. The formulas take into account short-channel effects and the variation of VTH and temperature. Using typical device parameters, it is shown that a simple guideline to optimize the power consumption is to set the ratio of maximum leakage power to total power about 30%. Extending the analysis, the future VLSI design trend is discussed. The optimum VDD coincides with the SIA roadmap and the optimum VTH for logic blocks at the highest temperature and at the lowest process variation corner is in the range of 0V~ 0.1V over generations. 10-4 10-5 Drain current [A] 10-6 L=0.5 m Measured 10-7 Conventional ( =1.57 V =0.27) TH Proposed formula ( =1.5 V =0.29) TH 0 0.5 1 Gate voltage [V] 1.5 I. Introduction Decreasing power consumption of VLSI's is getting one of the key design issues. Lowering

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