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(1973)
Real-time systems
- Publisher
- Springer Journals
- Copyright
- Copyright © 2000 by Kluwer Academic Publishers
- Subject
- Computer Science; Processor Architectures; Special Purpose and Application-Based Systems; Operating Systems; Computing Methodologies
- ISSN
- 0922-6443
- eISSN
- 1573-1383
- DOI
- 10.1023/A:1008145215849
- Publisher site
- See Article on Publisher Site
Abstract
This paper contributes a comprehensive study of a framework to bound worst-case instruction cache performance for caches with arbitrary levels of associativity. The framework is formally introduced, operationally described and its correctness is shown. Results of incorporating instruction cache predictions within pipeline simulation show that timing predictions for set-associative caches remain just as tight as predictions for direct-mapped caches. The low cache simulation overhead allows interactive use of the analysis tool and scales well with increasing associativity.
Journal
Real-Time Systems – Springer Journals
Published: Sep 23, 2004