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(2018)
Sentaurus device user manual
R. Narang, M. Saxena, Mridula Gupta (2017)
Analytical Model of pH sensing Characteristics of Junctionless Silicon on Insulator ISFETIEEE Transactions on Electron Devices, 64
Y. Lee, Ta-Chun Cho, K. Kao, P. Sung, F. Hsueh, P. Huang, C. Wu, Shu‐Han Hsu, W. Huang, H. Chen, Y. Li, M. Current, B. Hengstebeck, J. Marino, T. Buyuklimanli, J. Shieh, T. Chao, W. Wu, W. Yeh (2014)
A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing2014 IEEE International Electron Devices Meeting
D. Schroder (2005)
Semiconductor Material and Device Characterization: Schroder/Semiconductor Material and Device Characterization, Third Edition
Yao-Jen Lee, Ta-Chun Cho, P. Sung, K. Kao, F. Hsueh, F. Hou, Po-Cheng Chen, Hsiu-Chih Chen, C. Wu, Shu‐Han Hsu, Yi-Ju Chen, Yao-ming Huang, Y. Hou, Wen-Hsien Huang, Chih-Chao Yang, Bo-Yuan Chen, Kun‐Lin Lin, Min-Cheng Chen, C. Shen, G. Huang, Kun-Ping Huang, M. Current, Yiming Li, S. Samukawa, Wen-Fa Wu, J. Shieh, T. Chao, W. Yeh (2015)
High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications2015 IEEE International Electron Devices Meeting (IEDM)
(2015)
international technology roadmap for semiconductors itrs/, Semiconductor Industry Association
Malkundi Kumar, Chia-Ying Hu, K. Kao, Yao-Jen Lee, T. Chao (2015)
Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETsIEEE Transactions on Electron Devices, 62
D. Schroder (1990)
Semiconductor Material and Device Characterization
S. Grover (2016)
Effect of Transmission Line Measurement (TLM) Geometry on Specific Contact Resistivity DeterminationTheory of Computing Systems \/ Mathematical Systems Theory
J. Colinge, Chi-Woo Lee, A. Afzalian, N. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A. Kelleher, B. McCarthy, R. Murphy (2010)
Nanowire transistors without junctions.Nature nanotechnology, 5 3
Sung-Jin Choi, Dong-il Moon, Sungho Kim, J. Duarte, Yang‐Kyu Choi (2011)
Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless TransistorsIEEE Electron Device Letters, 32
7 shows the electrostatic discharge reliability comparison for all three devices, (a) TLP current, and (b) Maximum Lattice Temperature
Zhuojun Chen, Yongguang Xiao, M. Tang, Y. Xiong, Jianqiang Huang, Jiancheng Li, X. Gu, Yichun Zhou (2012)
Surface-Potential-Based Drain Current Model for Long-Channel Junctionless Double-Gate MOSFETsIEEE Transactions on Electron Devices, 59
Ajay (2019)
Modified Core-Shell Double Gate Junctionless MOSFET with High ON-State and Low Leakage CurrentsSilicon, 12
J. Colinge (2012)
Junctionless transistors
Publisher's Note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations
R. Trevisoli, R. Doria, M. Souza, S. Das, I. Ferain, M. Pavanello (2012)
Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire TransistorsIEEE Transactions on Electron Devices, 59
In this article, an investigation has been done to address the resistance and reliability issues with Conventional Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (Conv. JL DG MOSFET). Due to the uniform doping (concentration range is 1 × 1018 cm−3-1 × 1019 cm−3) in Conv. JL DG MOSFET, the contact resistance at source and drain region is large which degrades the performance of devices. The increment in doping of source and drain region reduces the contact resistance but simultaneously it increases leakage in Conv. JL DG MOSFET. To address above mentioned issues, a new architecture has been discussed which is called Core-Shell Channel (CSC) JL DG MOSFET. The CSC JL DG MOSFET is offering low leakage current with highly doped concentration of impurity in source and drain. The first time electrostatic discharge (ESD) reliability investigation has been done for any JL MOSFET and CSC JL DG MOSFET.
Silicon – Springer Journals
Published: May 28, 2020
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